November 1, 2016: The TRANSACT 2017 website is now live.
October 1, 2016: The Transact and WTTM workshops are merging this year.
The past decade has seen an explosion of interest in programming languages, systems, and hardware to support transactions, speculation, and related alternatives to classical lock-based concurrency. Recently, transactional memory has crossed two important thresholds. First, IBM and Intel are now shipping processors with hardware support for transactional memory (TM). Second, the C++ Standard Committee has been working intensively to integrate TM as a new language feature. On the other hand, the post-release discovery of an erratum in Intel’s hardware TM implementation has brought upfront the need for effective TM verification mechanisms. Overall, these developments highlight the demand for continued high quality transactional memory research.
In 2017, Transact will be merged with the Workshop on the Theory of Transactional Memory (WTTM); this will mark the twelfth Transact and ninth WTTM. Transact 2017, will provide a forum to present and discuss the latest research on all aspects of transactional computing. The scope of the workshop is intentionally broad, with the goal of encouraging interaction across the languages, architecture, systems, database, and theory communities. Papers may address implementation techniques, foundational results, applications and workloads, or experience with working systems. Environments of interest include the full range from multithreaded or multicore processors to high-end parallel and distributed computing platforms.
The workshop seeks papers on topics related to all areas of software, hardware, and formal foundations for transactional computing. Specific topics of interest include but are not limited to:
- Run-time systems
- Hardware support
- Applications, workloads, and test suites
- Experience reports
- Language mechanisms and semantics
- Formal semantics
- Memory models
- Transactions for non-uniform and non-cache coherent memory systems (e.g., NUMA, GPUs, RDMA, distributed transactions)
- Formal verification
- Speculative concurrency
- Conflict detection and contention management
- Debugging and tools
- Static analysis and compiler optimizations
- Checkpointing and failure atomicity
- Persistence and I/O
- Machine Learning and Transactional Memory
- Nesting and exceptions
- Impossibility results and lower bounds
- Concurrent data structures and algorithms
Papers should present original research. The final version of the accepted papers will appear on the workshop's web site. These papers will be available to the participants in electronic format during the workshop. Transact/WTTM does not publish proceedings, so accepted papers may appear in other venues as well. As transactional memory spans many disciplines, papers should provide sufficient background material to make them accessible to the broader community. Papers focused on foundations should indicate how the work can be used to advance practice; papers on experiences and applications should indicate how the experiments reinforce or reflect principles.
Please use EasyChair to submit a paper to TRANSACT!
Papers must be submitted in PDF, and be no more than 8 pages in standard two-column SIGPLAN conference format including figures and tables but not including references. Shorter submissions are welcome. The submissions will be judged based on the merit of the ideas rather than the length. Submissions must be made through the on-line submission site. Final papers will be available to participants electronically at the meeting, but to facilitate resubmission to more formal venues, no archival proceedings will be published, and papers will not be sent to the ACM Digital Library.
Authors will have the option of having their final paper accessible from the workshop website. Authors must be familiar with and abide by SIGPLAN's republication policy, which forbids simultaneous submission to multiple venues and requires disclosing prior publication of closely related work.
At the discretion of the program committee and with the consent of the authors, particularly worthy papers may be recommended for a special journal issue.
Registration information coming soon.
- Submission Deadline: December 16, 2016
- Author Notification: January 19, 2017
- Workshop: February 5, 2017
1:30-3:00 Session 1 (Chair: Irina Calciu)
- Performance Improvement via Always-Abort HTM (slides) Joseph Izraelevitz, Lingxiang Xiang, and Michael Scott
- Towards White-Box Modeling of Hardware Transactional (slides) Daniel Castro, Diego Didona and Paolo Romano
- Practical Experience with Transactional Lock Elision (slides) Tingzhe Zhou, Pantea Zardoshti and Michael Spear
3:00-3:30 break
3:30-5:00 Session 2 (Chair: Alexander Matveev)
- Cost of Concurrency in Hybrid Transactional Memory (slides) Trevor Brown and Srivatsan Ravi
- Combining HTM and RCU to Implement Highly Efficient Balanced Binary Search Trees (slides) Dimitrios Siakavaras, Konstantinos Nikas, Georgios Goumas and Nectarios Koziris
- Memory Management for Concurrent Data Structures on Hardware Transactional Memory (slides) Peter Pirkelbauer, Amalee Wilson, Hadia Ahmed and Reed Milewicz
- Paolo Romano, INESC-ID and Instituto Superior Técnico of Lisbon (Portugal)
- Aleksandar Dragojević, Microsot Research (co-chair)
- Idit Keidar, Technion (co-chair)
- Aleksandar Dragojević, Microsot Research (co-chair)
- Idit Keidar, Technion (co-chair)
- Irina Calciu, VMWare Research
- Pascal Felber, Université de Neuchâtel
- Guy Golan-Gueta, VMWare Research
- Alexey Gotsman, IMDEA
- Eshcar Hillel, Yahoo Research
- Petr Kuznetsov, INFRES, Telecom ParisTech
- Yossi Lev, Oracle
- Alexander Matveev, MIT
- Alessia Milani, University of Bordeaux
- Adam Morrison, Tel Aviv University
- Roberto Palmieri, Virginia Tech
- Ravi Rajwar, Intel
- Michael Spear, Lehigh University
- Xinmin Tian, Intel
- Osman Unsal, Barcelona Supercomputing Center
- Vasileios Trigonakis, Oracle/EPFL
- Pascal Felber, University de Neuchatel
- Justin Gottschlich, Intel Labs
- Dan Grossman, University of Washington
- Rachid Guerraoui, EPFL
- Tim Harris, Oracle Labs
- Maurice Herlihy, Brown University
- Eliot Moss, UMass
- Jan Vitek, Purdue University
- Michael Scott, University of Rochester
- Tatiana Shpeisman, Intel Labs
- Michael Spear, Lehigh University
Please contact the program chair